`ifndef DIV16_SIMPLE_V
`define DIV16_SIMPLE_V

`include "ALU16.v"

module Div16_Simple(
    input [15:0] dividend,    // 被除数
    input [15:0] divisor,     // 除数
    output [15:0] quotient,   // 商
    output [15:0] remainder,  // 余数
    output div_by_zero        // 除零标志
);
    
    // 除零检测
    assign div_by_zero = (divisor == 16'b0);
    
    // 处理符号
    wire dividend_sign, divisor_sign, quotient_sign;
    assign dividend_sign = dividend[15];
    assign divisor_sign = divisor[15];
    assign quotient_sign = dividend_sign ^ divisor_sign;
    
    // 取绝对值
    wire [15:0] dividend_abs, divisor_abs;
    wire [15:0] dividend_neg, divisor_neg;
    wire div_cout, dis_cout, div_overflow, dis_overflow;
    
    ALU16 abs_dividend(~dividend, 16'h0001, 1'b0, dividend_neg, div_cout, div_overflow);
    assign dividend_abs = dividend_sign ? dividend_neg : dividend;
    
    ALU16 abs_divisor(~divisor, 16'h0001, 1'b0, divisor_neg, dis_cout, dis_overflow);
    assign divisor_abs = divisor_sign ? divisor_neg : divisor;
    
    // 无符号除法 - 移位减法算法
    // 使用17个阶段，每个阶段处理一位
    
    wire [31:0] temp_remainder [16:0];
    wire [15:0] temp_quotient;
    
    // 初始化：余数 = {0, 被除数}
    assign temp_remainder[0] = {16'b0, dividend_abs};
    
    // 手动展开16次迭代（避免generate语法问题）
    
    // 迭代0 (处理最高位)
    wire [31:0] shifted_0 = temp_remainder[0] << 1;
    wire [15:0] sub_result_0;
    wire sub_cout_0, sub_overflow_0;
    wire can_subtract_0 = (shifted_0[31:16] >= divisor_abs);
    
    ALU16 subtract_0(shifted_0[31:16], divisor_abs, 1'b1, sub_result_0, sub_cout_0, sub_overflow_0);
    assign temp_quotient[15] = can_subtract_0;
    assign temp_remainder[1] = can_subtract_0 ? {sub_result_0, shifted_0[15:0]} : shifted_0;
    
    // 迭代1
    wire [31:0] shifted_1 = temp_remainder[1] << 1;
    wire [15:0] sub_result_1;
    wire sub_cout_1, sub_overflow_1;
    wire can_subtract_1 = (shifted_1[31:16] >= divisor_abs);
    
    ALU16 subtract_1(shifted_1[31:16], divisor_abs, 1'b1, sub_result_1, sub_cout_1, sub_overflow_1);
    assign temp_quotient[14] = can_subtract_1;
    assign temp_remainder[2] = can_subtract_1 ? {sub_result_1, shifted_1[15:0]} : shifted_1;
    
    // 迭代2
    wire [31:0] shifted_2 = temp_remainder[2] << 1;
    wire [15:0] sub_result_2;
    wire sub_cout_2, sub_overflow_2;
    wire can_subtract_2 = (shifted_2[31:16] >= divisor_abs);
    
    ALU16 subtract_2(shifted_2[31:16], divisor_abs, 1'b1, sub_result_2, sub_cout_2, sub_overflow_2);
    assign temp_quotient[13] = can_subtract_2;
    assign temp_remainder[3] = can_subtract_2 ? {sub_result_2, shifted_2[15:0]} : shifted_2;
    
    // 迭代3
    wire [31:0] shifted_3 = temp_remainder[3] << 1;
    wire [15:0] sub_result_3;
    wire sub_cout_3, sub_overflow_3;
    wire can_subtract_3 = (shifted_3[31:16] >= divisor_abs);
    
    ALU16 subtract_3(shifted_3[31:16], divisor_abs, 1'b1, sub_result_3, sub_cout_3, sub_overflow_3);
    assign temp_quotient[12] = can_subtract_3;
    assign temp_remainder[4] = can_subtract_3 ? {sub_result_3, shifted_3[15:0]} : shifted_3;
    
    // 迭代4
    wire [31:0] shifted_4 = temp_remainder[4] << 1;
    wire [15:0] sub_result_4;
    wire sub_cout_4, sub_overflow_4;
    wire can_subtract_4 = (shifted_4[31:16] >= divisor_abs);
    
    ALU16 subtract_4(shifted_4[31:16], divisor_abs, 1'b1, sub_result_4, sub_cout_4, sub_overflow_4);
    assign temp_quotient[11] = can_subtract_4;
    assign temp_remainder[5] = can_subtract_4 ? {sub_result_4, shifted_4[15:0]} : shifted_4;
    
    // 迭代5
    wire [31:0] shifted_5 = temp_remainder[5] << 1;
    wire [15:0] sub_result_5;
    wire sub_cout_5, sub_overflow_5;
    wire can_subtract_5 = (shifted_5[31:16] >= divisor_abs);
    
    ALU16 subtract_5(shifted_5[31:16], divisor_abs, 1'b1, sub_result_5, sub_cout_5, sub_overflow_5);
    assign temp_quotient[10] = can_subtract_5;
    assign temp_remainder[6] = can_subtract_5 ? {sub_result_5, shifted_5[15:0]} : shifted_5;
    
    // 迭代6
    wire [31:0] shifted_6 = temp_remainder[6] << 1;
    wire [15:0] sub_result_6;
    wire sub_cout_6, sub_overflow_6;
    wire can_subtract_6 = (shifted_6[31:16] >= divisor_abs);
    
    ALU16 subtract_6(shifted_6[31:16], divisor_abs, 1'b1, sub_result_6, sub_cout_6, sub_overflow_6);
    assign temp_quotient[9] = can_subtract_6;
    assign temp_remainder[7] = can_subtract_6 ? {sub_result_6, shifted_6[15:0]} : shifted_6;
    
    // 迭代7
    wire [31:0] shifted_7 = temp_remainder[7] << 1;
    wire [15:0] sub_result_7;
    wire sub_cout_7, sub_overflow_7;
    wire can_subtract_7 = (shifted_7[31:16] >= divisor_abs);
    
    ALU16 subtract_7(shifted_7[31:16], divisor_abs, 1'b1, sub_result_7, sub_cout_7, sub_overflow_7);
    assign temp_quotient[8] = can_subtract_7;
    assign temp_remainder[8] = can_subtract_7 ? {sub_result_7, shifted_7[15:0]} : shifted_7;
    
    // 迭代8
    wire [31:0] shifted_8 = temp_remainder[8] << 1;
    wire [15:0] sub_result_8;
    wire sub_cout_8, sub_overflow_8;
    wire can_subtract_8 = (shifted_8[31:16] >= divisor_abs);
    
    ALU16 subtract_8(shifted_8[31:16], divisor_abs, 1'b1, sub_result_8, sub_cout_8, sub_overflow_8);
    assign temp_quotient[7] = can_subtract_8;
    assign temp_remainder[9] = can_subtract_8 ? {sub_result_8, shifted_8[15:0]} : shifted_8;
    
    // 迭代9
    wire [31:0] shifted_9 = temp_remainder[9] << 1;
    wire [15:0] sub_result_9;
    wire sub_cout_9, sub_overflow_9;
    wire can_subtract_9 = (shifted_9[31:16] >= divisor_abs);
    
    ALU16 subtract_9(shifted_9[31:16], divisor_abs, 1'b1, sub_result_9, sub_cout_9, sub_overflow_9);
    assign temp_quotient[6] = can_subtract_9;
    assign temp_remainder[10] = can_subtract_9 ? {sub_result_9, shifted_9[15:0]} : shifted_9;
    
    // 迭代10
    wire [31:0] shifted_10 = temp_remainder[10] << 1;
    wire [15:0] sub_result_10;
    wire sub_cout_10, sub_overflow_10;
    wire can_subtract_10 = (shifted_10[31:16] >= divisor_abs);
    
    ALU16 subtract_10(shifted_10[31:16], divisor_abs, 1'b1, sub_result_10, sub_cout_10, sub_overflow_10);
    assign temp_quotient[5] = can_subtract_10;
    assign temp_remainder[11] = can_subtract_10 ? {sub_result_10, shifted_10[15:0]} : shifted_10;
    
    // 迭代11
    wire [31:0] shifted_11 = temp_remainder[11] << 1;
    wire [15:0] sub_result_11;
    wire sub_cout_11, sub_overflow_11;
    wire can_subtract_11 = (shifted_11[31:16] >= divisor_abs);
    
    ALU16 subtract_11(shifted_11[31:16], divisor_abs, 1'b1, sub_result_11, sub_cout_11, sub_overflow_11);
    assign temp_quotient[4] = can_subtract_11;
    assign temp_remainder[12] = can_subtract_11 ? {sub_result_11, shifted_11[15:0]} : shifted_11;
    
    // 迭代12
    wire [31:0] shifted_12 = temp_remainder[12] << 1;
    wire [15:0] sub_result_12;
    wire sub_cout_12, sub_overflow_12;
    wire can_subtract_12 = (shifted_12[31:16] >= divisor_abs);
    
    ALU16 subtract_12(shifted_12[31:16], divisor_abs, 1'b1, sub_result_12, sub_cout_12, sub_overflow_12);
    assign temp_quotient[3] = can_subtract_12;
    assign temp_remainder[13] = can_subtract_12 ? {sub_result_12, shifted_12[15:0]} : shifted_12;
    
    // 迭代13
    wire [31:0] shifted_13 = temp_remainder[13] << 1;
    wire [15:0] sub_result_13;
    wire sub_cout_13, sub_overflow_13;
    wire can_subtract_13 = (shifted_13[31:16] >= divisor_abs);
    
    ALU16 subtract_13(shifted_13[31:16], divisor_abs, 1'b1, sub_result_13, sub_cout_13, sub_overflow_13);
    assign temp_quotient[2] = can_subtract_13;
    assign temp_remainder[14] = can_subtract_13 ? {sub_result_13, shifted_13[15:0]} : shifted_13;
    
    // 迭代14
    wire [31:0] shifted_14 = temp_remainder[14] << 1;
    wire [15:0] sub_result_14;
    wire sub_cout_14, sub_overflow_14;
    wire can_subtract_14 = (shifted_14[31:16] >= divisor_abs);
    
    ALU16 subtract_14(shifted_14[31:16], divisor_abs, 1'b1, sub_result_14, sub_cout_14, sub_overflow_14);
    assign temp_quotient[1] = can_subtract_14;
    assign temp_remainder[15] = can_subtract_14 ? {sub_result_14, shifted_14[15:0]} : shifted_14;
    
    // 迭代15 (最后一次)
    wire [31:0] shifted_15 = temp_remainder[15] << 1;
    wire [15:0] sub_result_15;
    wire sub_cout_15, sub_overflow_15;
    wire can_subtract_15 = (shifted_15[31:16] >= divisor_abs);
    
    ALU16 subtract_15(shifted_15[31:16], divisor_abs, 1'b1, sub_result_15, sub_cout_15, sub_overflow_15);
    assign temp_quotient[0] = can_subtract_15;
    assign temp_remainder[16] = can_subtract_15 ? {sub_result_15, shifted_15[15:0]} : shifted_15;
    
    // 无符号结果
    wire [15:0] quotient_abs = temp_quotient;
    wire [15:0] remainder_abs = temp_remainder[16][31:16];
    
    // 处理符号
    wire [15:0] quotient_neg, remainder_neg;
    wire q_cout, r_cout, q_overflow, r_overflow;
    
    ALU16 neg_quotient(~quotient_abs, 16'h0001, 1'b0, quotient_neg, q_cout, q_overflow);
    ALU16 neg_remainder(~remainder_abs, 16'h0001, 1'b0, remainder_neg, r_cout, r_overflow);
    
    // 最终结果
    assign quotient = div_by_zero ? 16'h0000 : 
                     (quotient_sign ? quotient_neg : quotient_abs);
    assign remainder = div_by_zero ? dividend : 
                      (dividend_sign ? remainder_neg : remainder_abs);
    
endmodule

`endif
